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Ordering number : EN4374A
Thick-Film Hybrid IC
STK311-010
RDS Demodulation + Synchronization and Error Correction
Overview
The STK311-010 is a hybrid integrated circuit (HIC) for Radio Data System (RDS) applications which must conform to European Broadcasting Union (EBU) enforced recommendations. Since the Radio Data System (RDS) subjects every kind of data to multiplex broadcasting for FM broadcasts, the STK311-010 functions as a hybrid IC which demodulates the modulated signal's data, previously multiplexed to a RDS signal, matches synchronization and performs error detection and correction. By combining SC system and photoresist technology with folded board construction and incorporating Sanyo's unique insulated metal substrate technology (IMST) to the base, the STK311-010 has successfully been contained within a low-profile package.
Package Dimensions
unit: mm 4132
[STK311-010]
Applications
* Car stereos * Home stereos
Features
* On-chip 57 kHz BPF provides adjustment-free performance * On-chip 4 MHz ceramic oscillator * Supports RDS data demodulation system designs incorporating fewer external components * On-chip ARI-SK/DK decoder
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Operating temperature Storage temperature Symbol VCC max Topr Tstg Conditions Ratings 6.3 -30 to +85 -40 to +100 Unit V C C
Recommended Operational Voltage at Ta = 25Ct
Parameter Supply voltage Power supply voltage operating range Symbol VCC VCC OP Conditions Ratings 5 4.7 to 5.5 Unit V V
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N3096HA(OT)/10293YO 5-3279No. 4374-1/7
STK311-010 Operating Characteristics at Ta = 25C, VCC = 5V
Parameter Quiescent current Band-pass filter gain Symbol ICCO VGBPF f = 57 Hz f = 60 kHz (57 kHz = 0 dB) Band-pass filter selectivity f = 54 kHz (57 kHz = 0 dB) f = 38 kHz (57 kHz = 0 dB) PLL capture range RDS detection seisitivity SK detection seisitivity DK detection seisitivity RDS input dynamic range CR 5 mVrms, CW input 4 pin input voltage which sets 12 pin to low 4 pin input voltage which sets 11 pin to low 4 pin input voltage which sets 10 pin to low 4 pin maximum input signal (ARI + RDS) which sets 12 pin to low 4 pin maximum input signal (ARI) which sets 10 pin to low fOSC VOH VOL tCFS tRST *1 IOH = -50 A *1 IOH = -10 A *2 IOL = 10 mA *2 IOL = 1.8 mA Refer to Figure 1 Refer to Figure 2 30 9 -6 -6 Conditions min typ 26 12.5 -2.5 -3.5 -39 -0.9 +1.5 0.4 1.0 1.7 50 1.0 2.0 2.6 max 38 17 0 0 -33 Unit mA dB dB dB dB % % mVrms mVrms mVrms mVrms
DK input dynamic range VCO free-run frequency Output high level voltage
75 453 VCC - 1.2 VCC - 0.5
100 456 459
mVrms kHz V V 1.5 0.4 10 V V ms
Output low level voltage Ceramic oscillator stability time Reset time
Note: 1. DATA START, DATA OUT, CLOCK OUT 2. RECEIVE, CORRECTION, ERROR, DATA START, DATA OUT, CLOCK OUT
Other The STK311-010 supports HIC internal settings for all output signals of CLK OUT and DATA START. These are shown in the following table. Table 1 Output Signal Settings
Setting 1 2 3 4 Polarity of CLK OUT Negative edge trigger Negative edge trigger Positive edge trigger Positive edge trigger DATA START Output Every block Only 2nd block Every block Only 2nd block
Note: STK311-010 defaults to setting 1 though other settings are supported.
No. 4374-2/7
STK311-010 Internal Equivalent Circuit
Sample Application Circuit
Sample System Configuration
No. 4374-3/7
STK311-010 Pin Functions
Pin No. 1 2 3 4 5 9 10 11 12 13 Pin name OSC VCC AG INPUT MONI ID-ADJ DK-ID SK-ID RDS-ID DG Functions This pin is for connecting the VCO ceramic oscillator (456 kHz). This power supply pin is for LA2230 and LC7073 plus power supply. This ground pin is for connecting the analog system (LA2230) ground (GND). This is the input pin. This pin is for BPF (adjustment use) monitor output. This pin is for SK detection sensitivity adjustment use. Output pin for signaling existence of DK signal detection. When DK signal detection is possible, a low level output is enabled and when detection is not possible, a high level is established. Output pin for signaling existence of SK signal detection. When SK signal detection is possible, a low level output is enabled and when detection is not possible, a high level is established. Output pin for signaling existence of RDS signal detection. When RDS signal detection is possible, a low level output is enabled and when detection is not possible, a high level is established. This ground pin is for connecting the digital system (LC7073) ground (GND).
14
RESET
This pin is for reset input. Reset restart inputs a low level for more than 4 clock cycles. Schmitt type with an on-chip pull-up resistor.
15
CORR. SEL
Select input pin for error correction existence. This pin is for setting whether or not errors within RDS demodulation data are corrected or output as is. When set to 0, the correction function is disabled; a setting of 1 enables error correction. Error correction mode corrects up to 5 bits within 5 bit distance.
16
DATA START
Output configuration controlled from serial data output block data starting signal DS control input. CMOS type output pin with pull-up MOS transistor.
17
DATA OUT
Serial data output data CMOS type output pin with pull-up MOS transistor.
18
CLK OUT
Clock output. CMOS type output pin with pull-up MOS transistor.
19
OSC CHK
Pin for OSC 1 oscillation frequency check.
No. 4374-4/7
STK311-010 Relationship of RDS Demodulation Data (LA2230 Output) and LC7073 Output Data
* Serial data output from LC7073 (DATA OUT) is output 1 block slower than data received from LA2230/2231. Figure 3 Relationship of Demodulation Data and Output Data
Serial Data Output Format and Timing S E F OE OF A/B B1 and B0 : Start bit (defaults to 0) : Error flag Refer to table for flag settings : Correction flag : Offset E (defaults to 0, future expansion use) : Offset F (defaults to 0, future expansion use) : Group type version 0 : Version A 1 : Version B : Block number 00 : First block 01 : Second block 10 : Third block 11 : Fourth block : RDS data
Table 2 Error (E) and Correction (F) Flags Item No error Correction complete Uncorrectable E 0 0 1 F 0 1 1
D15 to D0
Figure 4
Serial Data Output Format and Timing
No. 4374-5/7
STK311-010 Control Input CORR.SEL Pin Read Timing Usually, this pin is used for checking pin states. However, the error correction can be activated using this control input at any time. During Synchronization Detection Pin status is read for every single bit of demodulation data from the RDS demodulation IC (indicated in the illustration by a down arrow ) and this continues for four times until the time that a single bit can be taken and read to the internal system.
Figure 5
Pin Read Timing During Synchronization Detection
After Synchronization Detection Pin status is read for every block header of demodulation data from the RDS demodulation IC (indicated in the illustration by a down arrow ) and this continues for four times until the time that a single bit can be taken and read to the internal system.
Figure 6 Data Characteristics
Pin Read Timing After Synchronization Detection
No. 4374-6/7
STK311-010
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1997. Specifications and information herein are subject to change without notice. No. 4374-7/7

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